1. Field of the Invention
The present invention relates to memory devices based on programmable resistance materials memory materials, including chalcogenide based materials and other phase change materials, and methods for operating such devices.
2. Description of Related Art
In general, system-on-a-chip (SOC) technology is the integration of multiple subsystems of an electronic system within a single integrated circuit, and may contain digital, analog, mixed-signal, and radio-frequency functions. The various types of subsystems that may be integrated within the integrated circuit include microprocessor and microcontroller cores, digital signal processors (DSPs), configurable logic units, memory blocks, timing sources, external interfaces, and power management circuits, among others. An SOC consists of both the hardware described above, as well as the software that controls the subsystems. The term “system-on-a-chip” may be used to describe complex application-specific integrated circuits (ASIC), where many functions previously achieved by combining integrated circuits on a board are not provided by one single integrated circuit. This level of integration greatly reduces the size and power consumption of the system, while generally also reducing manufacturing costs.
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
It has been observed that some phase change memory cells in the reset state experience a decrease in resistance over time to below a threshold value used to distinguish between the reset and set states, resulting in data retention problems and bit errors for those memory cells. For example, a memory cell in which an active region has been reset to a generally amorphous phase may over time develop a distribution of crystalline regions within the active regions. If these crystalline regions connect to form a low resistance path through the active region, when the memory cell is read a lower resistance state will be detected and result in a data error. See, Gleixner, “Phase Change Memory Reliability”, 22nd NVSMW, 2007. Similar issues can arise in other types of programmable resistance materials.
One attempt at addressing the data retention problems caused by the decrease in resistance over time is to maintain a relatively large margin between the set and reset states. However, in phase change memory, a relatively large margin typically requires a slow set operation and high reset current in order to obtain the large difference in resistance between the set and reset states. The relatively slow set speed and a high reset current limit the operational speed of the device, restricting the use of phase change based memory circuits as high speed memory.
Thus, circuits employing phase change based memory circuits typically also include other types of memory circuits in order to fulfill the memory performance requirements for the various functions of the integrated circuit. These different types of memory circuits typically include SRAM or DRAM memory circuits in order to provide high access speed memory for the integrated circuit. However, integration of different types of memory circuits for the various memory applications can be difficult and result in highly complex designs.
It is therefore desirable to provide programmable resistance memory based devices and methods for operating which address different memory performance requirements, including applications requiring high speed operation, while also addressing the issue of design integration.